Abstract
A novel 12.5Gbps quarter rate CDR is presented in this paper. For lock acquisition depends on the frequency tracking loop (FLL loop) and recovered clock jitter depends on the phase tracking loop (PLL loop) without one impacting the other, the CDR gets both short lock acquisition and low clock jitter. Moreover, a novel frequency band switch (FBS) is proposed, which switches the band of VCO. Meanwhile, the FBS ensures proper switching of dual loops to prevent false locking, without another lock detector, reducing the power consumption. Realized in 55-nm CMOS technology, the CDR consumes 15.2mW with a 1.2V supply.
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