A 12 mW ADPLL Based G/FSK Transmitter for Smart Utility Network in 0.18 ㎛ CMOS

Abstract

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in 0.18㎛ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 3.5 ㎟. The power consumption of the ADPLL is 12.43 ㎽. And, the power consumptions of the transmitter are 35.36 ㎽ and 65.57 ㎽ when the output power levels are -1.6 ㏈m and +12 ㏈m, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ㎰. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 ㎐. The phase noise of the ADPLL output at 7.8㎓ is -121.17 ㏈c/㎐ with a 1㎒ offset.