A 10 GHz delay line frequency discriminator and PD/CP based CMOS phase noise measurement circuit with −138.6 dBc/Hz sensitivity at 1 MHz offset

Abstract

This paper presents a delay line frequency discriminator (FD) and phase detector (PD)/charge pump (CP) based phase noise measurement (PNM) circuit to achieve wide bandwidth, great sensitivity and reliable integration at 10 GHz. PD/CP based phase noise detection makes it insensitive to environment and coupling noises. A delay-locked loop (DLL) is designed to align the PD input phases and a DC offset cancellation circuit is embedded to overcome circuit mismatches, which make the PNM self-calibrated. This PNM demonstrates −61/−81 dBc single tone sensitivity and −110.35/−138.60 dBc/Hz phase noise sensitivity at 100 kHz/1 MHz offset, respectively. The phase noise measurement bandwidth is 200 MHz, which is determined by the off-chip SAW filter bandwidth. This proof-of-concept design is fabricated in a 65 nm CMOS technology with the chip area of 1.5 mm × 1.3 mm. The core circuit consumes 15.2 mW power.