A 1.2 GSample/s Double-Switching CMOS THA With ${- }$62 dB THD

Abstract

Hold-mode feed-through is an important design problem, which plagues the classical switched-buffer track-and-hold amplifier (THA) topologies. The cross-coupled capacitor technique is a simple way of reducing hold-mode feed-through. However, the reduction in hold-mode feed-through is dependent on the matching between the cross-coupled capacitors and the inherent feed-forward capacitors. A double-switching switched-buffer THA is proposed, which has a switching input buffer. The proposed technique results in exceptional hold-mode isolation without the usage of the cross-coupled capacitor technique. Under Nyquist-rate sampling, 62 dB spurious-free-dynamic-range (SFDR), and 10 bit accuracy are achieved with input frequencies up to 800 MHz and 600 MHz respectively. Two prototype chips are designed in a 0.18 mum CMOS process. To maximize speed and dynamic range, the THA makes use of both 3.3 and 1.8 V devices, and uses 3.3 V analog supply voltage. Where necessary, 3.3 V devices cascode the 1.8 V devices for safe operation. The performance of the THA is comparable to most bipolar designs, both in speed and accuracy.