A 0.55mm2 16.9mW Fully Integrated 0-to-200MHz System BW Wireless Direct Sampling Receiver in 14nm FinFET

Abstract

In wireless communication systems, the direct conversion receiver (DCR) is widely used because of its simple implementation without image rejection filters and the demodulation of wideband RF signals [1-2]. Despite this simple architecture, it has the design burdens of a low jitter local oscillator (LO) and its associated mixers. Especially, to control the LO optimally with various frequency bands, it might require a wide LO frequency range and complex controls for analog circuitry. For a long time, the direct sampling receiver (DSR) has been considered attractive receiver architecture because of its digital-friendly architecture without a heavy design burden for the mixing operation. Although it can drastically simplify the analog frontend compared with that of the DCR, it requires a high speed and wide dynamic range ADC which was hard to be realized with low power. Thanks to the recent CMOS technology downscaling, the speed of successive-approximation register (SAR) ADC have been drastically improved, which shows the best power efficiency [3]. In addition, the power consumption for the digital signal processing has been significantly reduced with the downscaling. This recent advance opens a new opportunity for the wireless DSR. In previous works utilizing these architectural advantages, [4] has a poor antialiasing filter characteristic and sensitivity level. In addition, [5] adopted a sub-sampling concept, however the system requires a tight front-end module design for an aggressive band-pass filtering.