A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects

Suryanarayanan Subramaniam,Amlan Ganguly,Md Shahriar Shamim,Tanmay Shinde,Padmanabh Deshmukh,Mark Indovina

doi:10.1109/socc.2017.8226023

A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects

Suryanarayanan Subramaniam, Amlan Ganguly + Show 4 more

https://doi.org/10.1109/socc.2017.8226023

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Publication Date: Sep 1, 2017

Citations: 30

Affiliation: Rochester Institute of Technology

#On-off Keying Receiver #Wireless Interconnects + Show 8 more

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Abstract

Wireless interconnects are capable of establishing energy-efficient intra and inter-chip data communications. This paper introduces a circuit level design of an energy-efficient millimeter-wave (mm-wave) non-coherent on-off keying (OOK) receiver suitable for such wireless interconnects in 45-nm CMOS process. The receiver consists of a simple two-stage common source structure based Low Noise Amplifier (LNA) and a source degenerated differential Envelope Detector (ED) followed by a Base Band (BB) amplifier stage. Operating at 60GHz, the proposed OOK receiver consumes only 6.1mW DC power from a 1V supply while providing a data rate of 17Gbps and a bit-energy efficiency of 0.36 pJ/bit.

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