Abstract
This paper presents a 0.25μm HV-CMOS implementation of a Synchronous Inversion and Charge Extraction (SICE) interface circuit for piezoelectric energy harvesting. The bias-flip interfacing circuits which perform voltage inversion on the extremes of the voltage waveform have been proved effectively boosting the output power of piezoelectric energy harvesting. The proposed SICE interfacing circuit inverts the piezoelectric voltage on each extremum (bias flip action) for a given number of extremum occurrences, and then extracts the total electrostatic through the Synchronous Electric Charge Extraction (SECE) circuit. Thus, the SICE circuit is a combination of Synchronous Switch Harvesting on Inductor (SSHI) and the SECE circuits. It can achieve high power gain and be independent of loading impedance. The SICE interfacing circuit in TSMC 0.25μm HV-CMOS has been executed and taped-out. The post layout simulation results, including power consumption, circuit efficiency, and power gain will be presented in this paper.
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