A 0.1-f<inf>ref</inf> BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering

Abstract

In the design of a fractional-N PLL, the trade-off between in-band VCO noise and ΔΣ quantization noise constrains the choice of loop bandwidth. Various circuit schemes have been proposed to relax such constrains with noise canceling methods [1, 2] at the cost of significant extra power and chip area, and with FIR filtering techniques [3, 4] utilizing multiple charge pumps (CPs), PFDs and dividers. To reduce the ΔΣ quantization noise, fractional phase rotation [4] has been also a popular approach as an alternative to the dual modulus divider. However, high-resolution phase interpolators (PIs) suffer from nonlinearities due to random mismatches among phase steps and systematic imperfections in circuit operation when the interpolated vector approaches quadrant boundaries, and such nonlinearities eventually limit the amount of noise reduction in PI-based PLL. This work presents a 1GHz ΔΣ fractional-N PLL based on the noise filtering by FIR-embedded PI. The proposed PI scheme greatly improves phase linearity by a dual-referenced interpolation and realizes FIR filtering without using multiple CPs, PFDs, and dividers. The designed fractional-N PLL shows a comparable phase-noise performance to that of an integer-N PLL even with loop bandwidth of 0.1×f ref .