A 0.1–20 GHz Low-Power Self-Biased Resistive-Feedback LNA in 90 nm Digital CMOS

Abstract

In this letter, a 0.1-20 GHz low-power low noise amplifier (LNA) is presented. A novel self-biased resistive- feedback topology is proposed. Two inductors inside the feedback loop and a shunt-peaking inductor are exploited to extend the bandwidth. A PMOSFET with inductive degeneration is chosen as the load to boost the gain while maintaining low noise figure (NF) at high frequencies. A source-degeneration inductor is also introduced at the input transistor to ensure good input matching and stability over the entire bandwidth. All inductors are small due to the presence of feedback. The LNA was fabricated using a digital 90 nm CMOS process with 12.7 dB peak power gain, 3.3 dB minimum NF, and - 1 dBm peak input-referred third-order intercept point (IIP3). With 12.6 mW power consumption and 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, this wideband LNA may replace distributed amplifiers (DAs) in many applications.