7nm FinFET standard cell layout characterization and power density prediction in near- and super-threshold voltage regimes

Abstract

In this paper, we present a power density analysis for 7nm FinFET technology node, including both near-threshold and super-threshold operations. We first build a Liberty-formatted standard cell library by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. The layout of each cell then is characterized based on the lambda-based layout design rules for FinFET devices. Finally, the power density of the 7nm FinFET technology node is analyzed and compared with the state-of-the-art 45nm CMOS technology node for different circuits. Hspice results show that the power density of each 7nm FinFET circuit is at least 10 to 20 times larger than that of the same 45nm CMOS circuit in near- and super-threshold voltage regimes. Also the power densities of FinFET circuits are shown to be much higher than the limit of air cooling, which necessitates careful thermal management for the FinFET technology.