Abstract
Photon-count imaging has been proposed as a promising technology to realize image capture with noiseless readout and high dynamic range (HDR) [1]–[7]. In addition, for industrial and scientific applications, a global shutter exposure with motion artifact suppression is essential. A single-photon avalanche diode (SPAD) image sensor is well matched to the photon-counting architecture by shrinking the SPAD pixel size and stacking a logic chip with pixel-parallel Cu–Cu connections. A pixel-parallel photon counter, however, requires many counter bits in a pixel for HDR operation. This makes it difficult to shrink the pixel size and lower the power consumption, owing to the substantial number of SPAD activations under high light conditions [2]. Inter-frame mode switching between digital photon count and analog accumulation avoids the power increase under high light conditions, but it suffers from a dip in the signal-to-noise ratio (SNR) and/or motion artifact in reproducing an HDR image [3], [4]. An approach reducing SPAD activations under high light conditions can reduce the power consumption [5]–[7], but the combination of long- and short-exposure frames for HDR [5], [6] still suffers from the dip in SNR like conventional multi-exposure image sensors [8], even if these techniques can suppress motion artifacts owing to sub-frame readout.
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