Abstract
Describes a set of three processor chips capable of performing 32 and 64 bit floating point add/subtract, multiply, and divide operations. The chips can perform over one million scalar floating point operations per second, and over four million vector operations per second. The set is implemented in a four micron CMOS-on-sapphire process. Each chip has between 30000 and 60000 devices, and is about 250 mils on a side. Although asynchronous data paths are used within the chips, their interface to external system buses is synchronous with a maximum data bandwidth of over 70 Mbytes/s. The set has been designed for use in Hewlett-Packard computer and instrument systems.
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