Abstract
This paper presents a quarter rate clock/data recovery (CDR) circuit for plesiochronous serial I/O-links. This 2x-oversampled phase-tracking CDR, implemented in 90 nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s thanks to a data rate selection logic. A bit error rate <10-12 was verified up to 38 Gb/s using a 27-1 PRBS pattern. The CDR is able to track a maximum frequency deviation of plusmn615 ppm between incoming data and reference clock.
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