45-nm Planar bulk-CMOS 23-GHz LNAs with high-Q above-IC inductors

Abstract

Two 23 GHz low-noise amplifier (LNA) have been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNAs, the structure of cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging (WLP) technology. The fabricated one-stage LNA has a good linearity where the input 1 dB compression point (IP −1dB ) is −9.5 dBm and the input referred third-order intercept point (P IIP3 ) is +2.25 dBm. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated one-stage LNA has demonstrated a 4 dB noise figure (NF) and a 7.1 dB gain at the peak gain frequency of 23 GHz. Moreover, the fabricated two-stage LNA has the IP −1dB of −16 dBm and the P IIP3 of −4.2 dBm. It drains 9.3 mA from 1-V power supply. This two-stage LNA has demonstrated a 4.4 dB NF and a 11.6 dB gain at the peak gain frequency of 23.4 GHz. The fabricated one-stage LNA has the highest figure-of-merit (FOM). The experimental results have proved the suitability of 45 nm gate length planar bulk-CMOS devices for RF ICs above 20 GHz.