3D SiP with Organic Interposer for ASIC and Memory Integration

Abstract

To meet the requirements of the next high generation high-performance networking switches and routers, system integration based on the Three-dimensional (3D) System-in-Package (SiP) technology is being studied and developed. In this paper, we report the development of a 3D SiP using the organic interposer technology. A 3D SiP is designed and manufactured with a large size organic interposer with fine-pitch and fine-line interconnections. The organic interposer has a size of 38 mm x 30 mm x 0.4 mm. A high performance ASIC die measured in 19.1 mm x 24 mm x 0.75 mm is attached on top of the organic interposer along with four High Bandwidth Memory (HBM) DRAM die-stacks. The 3D HBM die-stack with a size of 5.5 mm x 7.7 mm x 0.48 mm includes one base buffer die and four DRAM-core dice which are interconnected with Through-Silicon-Vias (TSVs) and fine-pitch micro-pillars. Both the ASIC die and the HBM stacks are assembled to the organic interposer with the micro-pillar interconnection and a unique Chip to Chip (C2C) joining process developed. The organic interposer and the C2C joining enabled the ASIC and memory subsystem integration while overcoming the size limitation of the conventional silicon interposer that is due to the reticle size used in the wafer lithographic processing. Electrical performance of the ASIC-HBM memory interface and functionalities of the ASIC and HBM DRAM stacks as well as the open and short of critical interconnects are verified and tested using an application evaluation board fabricated.