3 - Sequential Logic Design

Abstract

This chapter describes the analysis and design of sequential logic. In contrast to combinational logic, whose outputs depend only on the current inputs, sequential logic outputs depend on both current and prior inputs. Sequential logic remembers information about prior inputs. This memory is called “the state of the logic.” Sequential circuits can be difficult to analyze and are easy to design incorrectly, hence the chapter describes only a small set of carefully designed building blocks. The most important element is the flip–flop, which receives a clock and an input, D, and produces an output, Q. The flip–flop copies D to Q on the rising edge of the clock and otherwise remembers the old state of Q. A group of flip–flops sharing a common clock is called a “register.” Flip–flops may also receive reset or enable control signals. Synchronous sequential circuits consist of blocks of combinational logic separated by clocked registers. The state of the circuit is stored in the registers and updated only on clock edges. Finite state machines (FSM) are also a powerful technique for designing sequential circuits.