Abstract

The clock frequency of high-performance processors in the high-voltage turbo/burst operation mode [1] is governed primarily by the RC-dominated global interconnects in the communication fabrics and NoCs, since the interconnect RC delay does not improve proportionally with logic gate delay at higher voltages. Prior current-mode and pre-emphasis techniques for improved interconnect throughput and energy efficiency [2]–[5] do not address the critical turbo/burst mode latency requirements, and do not consider tunability across a wide voltage-frequency operating range in high-performance processors. Their transmit/receive circuits with complicated data recovery and differential signaling incur major latency and wiring resource overheads, especially for shorter bus distances typical in NoCs. Previous hybrid current/voltage-mode signaling used expensive 4-inversion repeaters without reconfigurable resistive termination strength, and required multi-cycle windows for current-mode operation with limited power savings at high data activities [6]. Other techniques address scalability to lower supply voltages, but do not focus on the critical interconnect RC delay bottlenecks at high voltages [7]. In this paper, we present reconfigurable current/voltage-mode driver/repeater/receiver circuits for on-die global interconnects/busses, fabricated in 10nm CMOS, with transient current-mode operation, achieving: i) up to 38% lower delay/mm vs. voltage-mode operation, ii) 5x lower transient current-mode power vs. always-on current-mode operation at 100% data activity, iii) similar noise immunity as voltage-mode operation, iv) tunable current-mode configuration for optimized performance vs. energy across PVT corners, and v) up to 8x increased repeater distance.

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