Abstract
Asynchronous domino logic pipeline design is a latchless high throughput and low power design. In this design dual-rail domino gates are used to construct the stable critical data path and single-rail domino gates are used in non critical data paths. An 8x8 array style multiplier is used to evaluate this pipeline design. This proposed technique is general and can be used in all domino logic circuit designs. Now this can be implemented for higher order multipliers like 16x16.
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