16.5 DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching

Abstract

In-memory computing (IMC) processors show significant energy and area efficiency for deep neural network (DNN) processing [1–3]. As shown in Fig. 16.5.1, despite promising macro-level efficiency and throughput, there remain three main challenges to extending gains to system performance with a high integration level. First, most previous works had a fixed configuration and fixed size of IMC macros, and when the size of macro was smaller than the DNN layer's dimension, repetitive memory accesses were required for IA/OA, consuming >40% of IMC power. In the opposite case, macros experience underutilization. Second, previous eDRAM-based [4–6] IMCs showed even lower cell density than SRAM-based IMCs [1–3], owing to the area needed to realize a large cell capacitor for long retention time. Third, previous IMC processors [1], [2], [5] employed bit truncation to mitigate the ADC area overhead, incurring large quantization noise. Consequently, an IMC processor capable of adapting and optimizing its macro architecture for varying tasks with a high-density cell is required for higher system-level efficiency and throughput in DNN processing.