Abstract
Noise measurements of the 1/f in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two low noise CMOS processes of 2 /spl mu/m and 0.5 /spl mu/m technologies are compared and it is found that the more advanced process, with 0.5 /spl mu/m technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred and the power spectral density (PSD) of the drain current 1/f are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f of CMOS analog circuits.
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