Σχεδίαση αναλογικών ολοκληρωμένων φίλτρων χαμηλής τάσης τροφοδοσίας στο πεδίο του υπερβολικού ημίτονου

Abstract

This present Ph.D dissertation is focused its interest on the design of low voltage analog integrated circuits. Companding (compressing-expanding) systems are Externally Linear, Internally Non-linear (ELIN) processors with potential for low-voltage operation capability. In this direction novel topologies of companding filters in the Sinh-Domain are introduced. Τhe radical technological developments of microelectronics in the systems implementation with high reliability and performance, such as portable electronic devices for multimedia, communications and biomedical systems, demand the design of integrated circuits with reduced power consumption and thus low voltage supply. Integration of analog and digital circuits of systems-on-chip – (SoC) in order to be kept the low cost, directly affects the performance of the analog section, pointing forward the need for novel architectural design. One of the basic building blocks for circuit design is analog filters and their investigation in order to achieved large dynamic range, electronic tuning capability of their frequency characteristics which has gained a significant research effort toward these goals. At first, a new systematic method for designing Sinh-Domain filters is introduced. The proposed method offers the benefits of facilitating the design procedure of high-order Sinh-Domain filters using already introduced building blocks and of the absence of any restriction concerning the type and/or the order of the realized filter function. This is achieved by employing an appropriate set of complementary operators, in order to transpose the conventional functional block diagram representation of each linear operation to the corresponding one into the Sinh-Domain. In order to demonstrate the validity of the proposed systematic method, 3rd order leapfrog low-pass filter with a cut-off frequency at 10Hz which is typical for biomedical applications, has been realized following two alternative approaches and, also, a comparison has been performed among them and a conventional linear filter where the most important performance factors have been taken into account. Continuing, novel BiCMOS sinh-domain filter topologies, derived according to operational emulation, component substitution techniques and Linear Transformation of the corresponding 3rd-order passive prototype filters, with a cut-off frequency at 0.5 kHz and pass-band ripple 0.5dB, is proposed. This has been achieved by utilizing BiCMOS nonlinear ransconductor cells into the sinh domain. An attractive benefit of the proposed filter topologies is their capability for operating in high frequencies and a low-voltage environment. The performance of a leapfrog sinh-domain filter has been compared, using the Analog Design Environment of the Cadence software using AMS CMOS S35 0.35μm, with those of the corresponding log-domain and operational ransconductance amplifier (OTA)-C filters. Furthermore, the design of a family of Sinh-Domain universal biquad filters are introduced offering the benefits of low-voltage operation and, simultaneously, power efficient realizations in comparison with the corresponding already proposed biquads. Also, they have the capability for orthogonal adjustment between the resonance frequency and Q factor of the filter and these parameters could be also electronically adjusted through appropriate dc currents. Thus, they could be considered as attractive blocks for realizing high-performance analog signal processing systems. Finally, a Sinh-Domain topology for realizing the Non Linear Energy Operator (NEO) is introduced. For this purpose, a novel Sinh-Domain differentiator is proposed which offers the benefits of ultra low-voltage operation capability and electronic tuning of the realized time-constant. The whole system is also constructed from a four-quadrant current multiplier, realized by employing appropriately configured non-linear transconductors. Considering a single power supply voltage of 0.5V, the behavior of the proposed Sinh-Domain NEO realization has been simulated using the Analog Design Environment of the Cadence software using TSMC 130 nm design hit.